The present invention relates to an improved method and means for error checking in data transmission systems of the type wherein data bit groups are transmitted serial by group over a plurality of parallel lines between sending and receiving stations, but is also applicable to systems utilizing serial-by-bit transmission. In data transmission systems of the parallel type, it is known in the art to make use of parity bits transmitted simultaneously with the data bit groups to determine the presence of errors which can occur in the transmission. In most instances, the prior art teaches the use of either even parity checking or odd parity checking of the data. In some instances, even parity checking is used for one complete record of data bit groups and odd parity checking is used for the next succeeding record of data bit groups.
Another means for checking for transmission errors in transmission systems of this type is referred to as longitudinal redundancy checking (LRC) wherein a predetermined number of data bit groups are transmitted followed by a longitudinal redundancy check bit group. This LRC check bit group is obtained for each bit position in the data bit group by counting the number of bits transmitted between each LRC bit group and determining the even or odd number of bits counted. Then a logical one or zero bit is assigned to the LRC bit group, depending upon whether even or odd checking is selected for use. At the receiving station, the data bit groups followed by the LRC group are fed into an LRC checking circuit to determine whether or not errors have occurred. Parity error checking and LRC checking and the combination of both are frequently used in data transmission systems to determine the existence of a large number of potential errors that can be created.
In the prior art, if a higher degree of error checking is desired, it is common to use a cyclic redundancy checking (CRC) algorithm to find a very high percentage of the possible errors which can occur.
The cost of the apparatus at the transmitting and receiving stations for CRC checking is very expensive in relation to the cost of both parity checking circuitry and LRC checking circuitry. Hence, in most situations, CRC checking is not used in parallel data transmission systems.
It has been found that by using apparatus which combines the conventional parity checking circuits and the LRC circuits in a distinctive way a very high percentage of the possible errors can be detected, substantially approaching the checking ability of the CRC implementation by merely assigning odd and even parity to succeeding groups of bits that are transmitted.
It is therefore an object of the present invention to provide an improved error checking mechanism for parallel data transmission systems which is low in cost but which approaches the error checking capabilities of CRC checking mechanisms and that can be used with serial data transmission systems, as well.
As stated, the principles of the present invention can be utilized in conjunction with data transmission systems wherein data is transmitted in a serial-by-bit fashion rather than in parallel. However, the cost advantages of the present system in comparison with the cost of the CRC checking mechanisms may not be as great as that encountered in a parallel transmission system. There may be some circumstances such as in a system that accommodates both parallel and serial transmission for utilizing the even-odd parity checking scheme described herein in conjunction with commonly shared logic and then similar cost advantages should accrue.